It is quite common during the operation of a computer for a number of sequential memory locations to be addressed. For example, during a direct memory access (DMA) transfer, a block of data will be transferred to or from an addressable memory space. To address each memory cell, the starting address and the count (number of sequential locations) are provided. The starting address is placed on the address bus and the first data element is transferred. The address is then automatically incremented as each sequential memory location is addressed. This continues until the number of memory locations addressed equals the count.
Counters have been used in the past to hold the current address. When the current address cycle is complete, a signal is sent to the counter to increment the address stored therein. The counter is then incremented and the next address cycle commences. A disadvantage of using counters in such an application is that they are relatively slow. Since the time required to increment the current address for each address cycle is cumulative such delays can adversely affect system performance.
Another disadvantage of counters is that they are relatively large. This is a particular problem where several counters are required. For example, indirect addressing may require one counter to track the addresses of data blocks stored in a memory map table (hereinafter referred to as a link table) and another counter to track the addresses of data within each data block. As a further example, a number of DMA chips are designed to handle more than one data storage device. Each device has a dedicated channel, with each channel requiring its own counters. Thus, the number of required counters for tracking addresses can escalate depending on the application. The larger number of counters on a chip requires more chip die area.